1A Statistical Modeling and Optimization Methodologies | |
1B System-level Energy Management | |
1C Equivalence Verification | |
1D Advances in Interconnect Analysis | |
2A Soft Error Rate Analysis | |
2B Application Specific Memory and Processor Architecture Design Techniques | |
2C Embedded Tutorial: The Care & Feeding of Your Statistical Static Timer | |
3A Crosstalk-Aware Timing and Noise Analysis | |
3B System Software Optimizations | |
3C New Directions in Verification | |
3D Algorithms and Modeling Techniques for Bio and Nano Technologies | |
4A Developments in Timing Analysis and Optimization | |
4B Energy Efficiency and Interconnect Design | |
4C Floorplanning for Advanced Technologies | |
4D Robust Design Tools | |
5A Embedded Tutorial: Variability Impact on Design | |
5B Architectural Issues in System Synthesis | |
5C Integrated Placement Applications | |
5D Novel Directions in Logic Synthesis | |
6A Embedd Tutorial: World-level Methods in Formal Verification | |
6B Interconnect Coding and Optimization | |
6C Statistical Timing Methods | |
6D New Methods in Power Grid Analysis | |
7A Advances in SAT-based verification | |
7B Power and Layout-Driven Logic Optimization | |
7C Advances in Floorplanning and Placement | |
7D Programmable Fabrics for Structured Design | |
8A New Issues in Clocking | |
8B Innovative Models/Methods in Analog and Digital Diagnosis | |
8C Estimation and Management of Design Metrics | |
8D Advanced Analog/RF Macromodeling and Simulation | |
9A Estimation Techniques for Physical Design | |
9B Timing Model Validation and Efficient on-chip test compression | |
9C Embedded Tutorial: Emerging Technologies on the Design-Manufacturing Interface | |
| 9C.1 Design/Process Learning from Electrical Test. |  |
| 9C.2 Backend CAD Flows for "Restrictive Design Rules" |  |
9D OptimizationTechniques for FPGAs and Reconfigurability | |
10A Innovative Methods in High-Level Design | |
10B Power Analysis and Optimization | |
10C Routing | |
10D Analog Sizing and Optimization | |
11A Variational Analysis of Interconnects | |
11B Test Genearation for New Fault Models and Circuits | |
11C Embedded Tutorial: Transaction Level Modeling in System Design | |
11D Hierarchical Mixed-Signal Modeling and Design | |