1A Memory and Arithmetic Optimizations 1B Design Manufacturing Interaction 1C Detailed Placement 1D Digital, Analog, and RF Test 2A Embedded Tutorial: Design Trends 2B Physical Design for Manufacturing 2C Large-Scale Layout Techniques 2D Novel Ideas in Logic Synthesis 3A Embedded Tutorial: Design Opportunities and Challenges with Double-Gated Device 3B Routing and Application Specific NoC Architectures 3C Memory Driven Code and Architecture Optimizations 3D Exploiting Arithmetic Constructs in Verification 4A Buffers and Voltage Islands 4B Sequential Circuit Optimization 4C Power Grid Verification 4D Nanoelectronics 5A Variability in Design 5B Efficient Analog Design Space Exploration Techniques 5C Dynamic Voltage Scaling 5D Biochips and DNA-Based Nanofabrication 6A Efficient Simulation and Synthesis Methodologies for Analog Circuits 6B Technology Mapping and Timing Analysis 6C Power Aware System Architecture and Software Optimizations 6D Cellular Array Architectures 7A Variability Aware Clocking 7B Oscillator Analysis 7C Power Noise and Thermal Issues 7D Nanocomputing 8A Extraction and Modeling for Interconnect Structures 8B Timing and Power Optimization 8C System-Level Variability Modeling 8D Routing 9A New Frontiers in High-Level Synthesis 9B Advances in Model Order Reduction Approaches 9C Statistical Timing Analysis 9D Problem Structure in Formal Verification 10A Analytical Placement 10B Embedded Tutorial: Hardware and Software Design of Energy-Efficient Sensor Platforms 10B Embedded Tutorial: Hardware and Software Design of Energy-Efficient Sensor Plat 10B Embedded Tutorial: Hardware and Software Design of Energy-Efficient Sensor Platforms Embedded Tutorial: Hardware and Software Design of Energy-Efficient Sensor Plat 10C Improving the Accuracy of Static Timing Analysis 10D Embedded Tutorial : Formal Equivalence Checking Between System-Level Models an 11A Embedded Tutorial: Emergent Communications 11B Addressing Emerging Challenges for SoCs 11C Statistical Optimization 11C.1 Parametric Yield Maximization using Gate Sizing based on Efficient Statistical Power and Delay 11C.2 Gate Sizing Using Incremental Parameterized Statistical Timing Analysis 11C.3 Statistical Gate Sizing for Timing Yield Optimization 11D Making Model Checking Practical