1A Parasitic Simulation and Modeling 1A.1 Stable and Compact Inductance Modeling of 3-D Interconnect Structures 1A.2 A Fast Order Block Structure Preserving Model Order Reduction for Inverse Inductance Circuits 1A.3 Fullwave Volumetric Maxwell solver using Conduction Modes 1B Post-Placement Optimization Techniques 1B.1 Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robus 1B.2 Optimal Useful Clock Skew Scheduling In the Presence of Variations Using Robust ILP-Formulation 1B.3 State Re-Encoding for Peak Current Minimization 1C Variation Modeling 1C.1 A Statistical Framework for Post-Silicon Tuning Through Body Bias Clustering 1C.2 A Gate Delay Model Focusing on Current Fluctuation over Wide-Range of Process and Environmental 1C.3 Practical Variation-Aware Interconnect Delay and Slew Analysis for Statistical Timing Verificat 1C.4 Analysis and Modeling of CD Variation for Statistical Static Timing 1D Embedded Tutorial: From Dual to Multi to Many Core - Opportunities and Challeng 1D.1 From Dual to Multi to Many Core - Opportunities and Challenges for Supporting the New Exponenti 2A Embedded Tutorial: UML and SystemC for Industrial ESL Design - Basic Principles 2A.1 UML 2.0 for HW/SW Co-Design 2A.2 An SOC Co-Design Flow Based on UML and SystemC 2B Efficient Delay Test Generation 2B.1 On Bounding the Delay of a Critical Path 2B.2 A Delay Fault Model for At-Speed Fault Simulation and Test Generation 2B.3 Efficient Boolean Characteristic Function for fast Timed ATPG 2B.4 Exploring Linear Structures of Critical Path Delay Faults to Reduce Test Efforts 2C Power Grid Analysis and Design 2C.1 Fast Decap Allocation Based on Algebraic Multigrid 2C.2 Precise Identification of the Worst-Case Voltage Drop Conditions in Power Grid Verification 2C.3 Importance of Volume Discretization of Single and Coupled Interconnects 2C.4 Handling Inductance in Early Power Grid Verification 2D Optimization Techniques for Different Target Technologies 2D.1 Mapping Arbitrary Logic Functions into Synchronous Embedded Memories For Area Reduction on FPGA 2D.2 Factor Cuts 2D.3 An Efficient Technique for Synthesis and Optimization of Polynomials in GF(2^m) 2D.4 Cost-Aware Synthesis of Asynchronous Circuits Based on Partial Acknowledgement 3A Placement and Floorplanning 3A.1 A Revisit to Floorplan Optimization by Lagrangian Relaxation 3A.2 Fast Wire Length Estimation by Net Bundling for Block Placement 3A.3 Fast and Robust Quadratic Placement Combined with an Exact Linear Net Model 3A.4 A High Quality Analytical Placer Considering Preplaced Blocks and Density Constraint 3B Digital and RF Test and Reliability 3B.1 Testing Delay Faults in Asynchronous Handshake Circuits 3B.2 A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-Drop Effects 3B.3 Design Optimization for Single-Event Upset Robustness Using Simultaneous Dual-VDD and Sizing Te 3B.4 Enhanced Error Vector Magnitude (EVM) Measurements for Testing WLAN Transceivers 3C Statistical Timing Analysis 3C.1 A Linear-Time Approach for Static Timing Analysis Covering All Process Corners 3C.2 A Framework for Statistical Timing Analysis using Non-Linear Delay and Slew Models 3C.3 An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis 3C.4 A New Statistical Max Operation for Propagating Skewness in Statistical Timing Analysis 3D Power and Performance Optimizations on System Level Design 3D.1 Cache Miss Clustering for Banked Memory Systems 3D.2 A Bitmask-based Code Compression Technique for Embedded Systems 3D.3 Allocation Cost Minimization for Periodic Hard Real-Time Tasks in Energy-Constrained DVS System 3D.4 Application-Specific Customization of Parameterized FPGA Soft-Core Processors 4A Analog Simulation and Verification 4A.1 TP-PPV: Piecewise Nonlinear, Time-Shifted Oscillator Macromodel Extraction For Fast, Accurate P 4A.2 Verification of Analog/Mixed-Signal Circuits Using Labeled Hybrid Petri Nets 4A.3 PPV-HB: Harmonic Balance for Oscillator/PLL Phase Macromodel 4B Self Adaptation and Physical Awareness in High-Level Synthesis 4B.1 Loop Pipelining for High-Throughput Stream Computation Using Self-Timed Rings 4B.2 Thermal-Induced Leakage Power Optimization by Redundant Resource Allocation