1A Parasitic Simulation and Modeling 1B Post-Placement Optimization Techniques 1C Variation Modeling 1D Embedded Tutorial: From Dual to Multi to Many Core - Opportunities and Challeng 2A Embedded Tutorial: UML and SystemC for Industrial ESL Design - Basic Principles 2B Efficient Delay Test Generation 2C Power Grid Analysis and Design 2D Optimization Techniques for Different Target Technologies 3A Placement and Floorplanning 3B Digital and RF Test and Reliability 3C Statistical Timing Analysis 3D Power and Performance Optimizations on System Level Design 4A Analog Simulation and Verification 4B Self Adaptation and Physical Awareness in High-Level Synthesis 4C Advances in Performance Modeling for Interconnect and Memory 4D Embedded Tutorial: Design and CAD Challenges in 45nm CMOS and Beyond: From Fron 5A Analog Design Automation Techniques 5B Challenges on System Level Interconnection 5C Placement Optimization: Timing, Noise, and Power 5D Timing and Power Analysis 6A Thermal and Variability Issues in Architectures 6B Embedded Tutorial: Automation in Mixed-Signal Design: Reality Check and the Nano Challenge 6C Global Routing 6D Emerging Topics in Signal Integrity and Reliability 7A Fault-Tolerant Energy Minimization Techniques for Real-Time Embedded Systems 7B Emerging Issues in Contemporaneous System Level Design 7C Clock and Buffer Synthesis 7D Thermal Analysis for the Nano Scale 8A Advances in Embedded System Design 8B Architectural Design Techniques for High Performance and Robustness 8C Manufacturability and Power in Layout 8D Embedded Tutorial: Emerging Nanoelectronics: Prospects, State of the Art, and O 9A Technology Driven Layout Methodologies 9B Novel FPGA Architectures, Techniques, and Designs 9C Specification and Architecture Challenges in High-Level Synthesis 9D Defect Tolerance for Nanoscale Architectures 10A Dynamic Power Management 10B Advances in Model Checking 10B.1 Stepping Forward with Interpolants in Unbounded Model Checking 10B.2 Decomposing Image Computation for Symbolic Reachability Analysis Using Control Flow Information 10B.3 Automatic Memory Reductions for RTL-Level Verification 10B.4 Accelerating High-level Bounded Model Checking 10C Novel Interconnect Methodologies 10D Embedded Tutorial: Integrating Nanoelectronics, Biotechnology and MEMS/NEMS 11A Embedded Tutorial: Variability and Yield Improvement - Rules, Models, and Char 11B Accelerating Verification 11C Model Order Reduction and Parametric Analysis 11D Design and Modeling of Molecular-Scale Systems 5E Robustness and Reliability in Design 6E Design to Enable Verification 7E Mixed Signal Design Experiences