 1A Advances in Parasitic Extraction and Variability Modeling | |
| 1B Networks-on-Chip and Latency-Insensitive Systems | |
| 1C Power Grid Analysis | |
| 1D Synthesis and Verification of Quantum Circuits | |
| 2A Connecting Physical Challenges and Design Approaches | |
 2B Analytical Techniques for Physical Optimization | |
|  2B.1 Monte-Carlo Driven Stochastic Optimization Framework for Handling Fabrication Variability | |
| 2B.2 Gate Sizing by Lagrangian Relaxation Revisited | |
| 2B.3 An Efficient Algorithm for Statistical Circuit Optimization Using Lagrangian Relaxation | |
| 2B.4 Unified Adaptivity Optimization of Clock and Logic Signals | |
| 2C Logic Synthesis | |
| 2D Memory Optimization and System-Level Timing | |
| 3A Resilient and Regular Circuits | |
| 3B 3-D Integration Challenges | |
| 3C Applications of SAT and QBF | |
| 3D Embedded Tutorial: Physical Synthesis Comes of Age | |
| 4A High Quality Testcases for Verification | |
| 4B Advances in Embedded Systems | |
| 4C Can Nano-Photonic Silicon Circuits Become an Intra-Chip Interconnect Technology | |
| 4D Designers' Perspective: Memory Design Challenges in Sub-65-nm Technologies | |
| 5A Scaling Formal Verification | |
| 5B Advances in Statistical Timing Analysis and Optimization | |
| 5C Sequential Synthesis and FPGA Mapping | |
| 5D Designers' Perspective: High Speed I/O | |
| 6A Advances in Routing and Clock Design | |
| 6B Improving Delay Test Generation and Performance Predictors | |
| 6C High Level Synthesis | |
| 6D Analog Circuit Optimization | |
| 7A Global Routing | |
| 7B Test Compression and Test Power | |
| 7C Gate-level Physical Synthesis | |
| 7D Designers' Perspective: Foundry and Circuit Designer Communication | |
| 8A Interconnect Modeling and Optimization | |
| 8B Embedded Tutorial: Formal verification at Higher Levels of Abstraction | |
| 8C Floorplanning | |
| 8D System-level Synthesis and Interconnect Design | |
| 9A Advances in Model Order Reduction Techniques For Interconnect Analysis | |
| 9B Embedded Tutorial: MOSFET Modeling for 45nm & Beyond | |
| 9C Voltage Assignment in Floorplanning | |
| 9D Variation-Tolerant Circuits | |
| 10A Advanced Models for Static Timing Analysis | |
| 10B Variation Aware Timing Verification | |
| 10C Reliability-Driven Modeling and Analysis for Deep Submicron Technologies | |
| 10D Design Automation and Defect Tolerance Techniques for Emerging Technologies | |
| 11A Leakage Power Reduction | |
| 11B Power Modeling and Optimization | |
| 11C Improving Planarity and Patterning | |
| 11D Model Order Reduction for Parameterized and Non-Linear Systems | |