00 Sunday Panel: CAD for High-End Design: Help, Hope or Hype? 1A Interconnect-Centric SoC Design 1B Energy Optimization using Dynamic Voltage Scaling for Embedded Systems 1C New Opportunities in High-Level Synthesis 1D New Ideas in Placement and Floorplanning 2A Improvements in SoC Testing 2B Electrical and Power Models - System to Transistor Level 2C Embedded Tutorial: Design and CAD Challenges for sub-90nm CMOS Technology 3A Emerging Techniques in Dynamic Verification 3B Delay and Signal Modeling for Timing Analysis 3C Software Techniques for Energy and Performance Optimization in Embedded Systems 3D Optimization of Global Interconnects 4A Numerical Methods for Analog Optimization and Analysis 4B CAD Algorithms for Emerging Technologies 4C Design Techniques for Customized Processors 4D New Improvements in Placement 5A Optimizations for Verification Engines 5B System Design Concepts 5C Analog Design and Methodology 5D Routing 6A Automatic Abstraction for Formal Verification 6A.1 Improving Ariadne's Bundle by Following Multiple Threads in Abstraction Refinement 6A.2 Iterative Abstraction using SAT-based BMC with Proof Analysis 6A.3 Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits 6B Embedded Tutorial: System Level Design and Verification using a Synchronous Lan 6C Nonlinear Modelling of Analog and Optical Systems 6D Timing and Tradeoffs in Placement 7A Simulation at the Nanometer Scale 7B Energy Issues in Systems Design 7C Constraint Driven High-Level Synthesis 7D Optimal Interconnect Synthesis and Analysis 8A Memory Testing 8B Statistical Static Timing - I 8C Power-Aware Design 8D Interconnect Reduction 9A Embedded Tutorial: Mixed Signal DFT: A Concise Overview 9B Embedded Tutorial: Manufacturing-Aware Physical Design 9C Cool Topics in Logic Synthesis 9D Graph Algorithmic Approaches to EDA Problems 10A Parametric Considerations in Test Schems 10B Power-Grid and Substrate Analysis 10C Hot Topics in Logic Synthesis 10D Interconnect Modeling 11A Test Data Reduction Techniques 11B Embedded Tutorial: Formal Methods for Dynamic Power Management 11C Embedded Tutorial: Large-Scale Circuit Placement: Gap and Promise 11D Statistical Static Timing - II 99 Monday Panel: Semiconductor Slowdown: Who Will Blink First?